CARAVELAnalog & mixed-signal IC design / Porto, Portugal
RF and Mixed-Signal IP, spec to layout.
RF front-ends and SerDes are where we spend most of our time, with PMIC, ESD and the analog blocks around them. Send us your spec and we’ll come back to you within a couple of days.
FLOORPLANHover any block. The panel is an azulejo — the pad ring is its cercadura, and every block is a unit cell.
01 / Capabilities
What we take on
RF and SerDes front-ends, PMIC, ESD and the general analog blocks around them. Block and subsystem level, architecture study through to final layout delivery.
Wireless front-ends
Sub-GHz through 6 GHz, transmit and receive. Link budgets, blocker and reciprocal-mixing analysis, and a power budget built around burst current rather than average.
- IoT RF, BLE, 802.15.4
- PAs, LNAs, mixers, filters
- S-parameter cascade & matching
- Battery and pulse-load analysis
Serialiser & deserialiser front-ends
Transmit and receive front-ends for high-speed links. Equalisation, impedance and return loss held inside spec across every FFE tap setting.
- SST drivers, FFE, ZQ calibration
- CTLE, DFE and half-rate CDR
- Jitter and eye-closure budgets
- Channel and package co-design
Power management
Regulators and references for rails that can't tolerate noise. You get the PSRR curve across your band, the noise budget, and the dominant contributor named.
- FVF and EA-assisted LDOs
- Bandgaps, PTAT, trim networks
- DC-DC controllers & sequencing
- Noise budgets down to nV/√Hz
Protection & signoff
Protection designed with the pad, not bolted on afterwards. Domain-crossing analysis, clamp placement and the bus resistance that decides whether you pass.
- HBM, CDM per JEDEC JS-002
- T-coil networks for high-speed pads
- Latch-up, EM/IR, antenna
- DRC / LVS / PEX to tapeout
PLLs & oscillators
Integer and fractional-N synthesisers, analog and all-digital. The jitter budget ships with the design, and loop bandwidth is chosen against it.
- LC and ring DCOs
- Back-gate tuning in FD-SOI
- Clock distribution & deskew
- Phase noise and PSIJ analysis
Converters & analog front-ends
DACs, SAR ADCs and front-ends sized to your system, with headroom budgeted before the first transistor is placed.
- Current-steering and R-2R DACs
- SAR ADCs
- TIAs and programmable gain
- Matching, layout centroid, trim
Flow, PDK & CAD
The flow is standing before the first schematic is drawn. Foundry PDKs, corner and Monte Carlo setups, and regression scripts you can run yourself — results that reproduce on your machines, not only on ours.
- Virtuoso, Spectre / APS, ADE Explorer
- Calibre DRC / LVS / PEX, Quantus
- OCEAN and Python regression decks
- PDK, cellview and setup under version control
Schedule & delivery
One named engineer owns the block and answers your mail. Weekly written notes covering what moved, what didn't and what's at risk, against a schedule with real dates in it.
- Fixed scope, schedule and price up front
- Reviews at schematic, layout and signoff
- Version-controlled deliverables, tracked issues
- NDA, licensing and escrow settled early
Digital design
In build. Synthesis, place-and-route and digital verification alongside the analog flow, so a mixed-signal top level can be closed in one place rather than split across two houses.
- Synthesis, place-and-route, STA
- Mixed-signal top-level integration
- Digital verification
02 / How we work
Spec to silicon
Six stages, each with a defined deliverable. Most projects reach us partway in — tell us where you are and we pick it up there.
Spec review
We read your specification line by line and come back with the contradictions, the risks, and a fixed scope with a schedule and a price. Free, and back within three working days.
Architecture and budgets
Topology selected with the numbers attached — noise, PSRR, headroom, area and current allocated per block before any schematic exists. You get the budget spreadsheet.
Schematic and simulation
Design across corners, temperature and mismatch. Testbenches are built to be handed over and re-run by your team, with the methodology written down.
Layout and extraction
Analog layout done by the engineer who designed the circuit. Post-layout closure against the same testbenches, with every delta explained.
Verification and signoff
DRC, LVS, antenna, EM/IR and reliability. A signoff report stating what was checked, at which corners, and what was waived and why.
Tapeout and bring-up
Integration support through tapeout, then a bench plan for first silicon. We stay reachable when the parts come back.
Digital designIncoming
We are building out synthesis, place-and-route and digital verification so mixed-signal top levels can be closed under one roof. Not open for booking yet — ask us about timing if it affects your schedule.
03 / Selected work
Recent projects
IoT RF transmit and receive chain
Low-noise LDO
T-coil for SerDes with ESD compliance
Let's talk about your project?
Send us your spec →04 / About us
Professionals, no handoffs
Caravel is a professional analog design house in Porto.
We run a small number of projects at a time. You get named engineers, a schedule you can hold us to, and documentation your team can maintain.
- BasedPorto, Portugal. Work stays in the EU. GDPR by default; we sign to your jurisdiction on request.
- OverlapWET / WEST. A full working day with European clients, a long morning overlap with the US East Coast.
- EngagementFixed-scope block delivery, milestone-based subsystem work, or retained capacity by the month.
- IPYou own everything we draw. No background IP claims, no licence-back, no reuse across clients.
- HandoverGDS, schematics, testbenches, budget models and a written design guide. Not a black box.
- ResponseSpec review back within three working days, with scope, schedule and price.
- LanguagesPortuguês, English.
05 / Careers
Three ways in
If you wan't to work for a fast growing start-up with a lot of interesting projects and opportunities to grow, this is the company for you.
Analog IC design
Take a block from specification to signed-off schematic. You own the topology choice, the budgets behind it, and the corners it has to survive.
- Topology selection with budgets attached
- Corner, temperature and mismatch closure
- Testbenches built to be handed over
Analog IC layout
Draw the blocks our designers design — and, more often than not, design them further. Matching, shielding and current density are decisions, not clean-up.
- Common-centroid and matched structures
- Shielding, current density, EM/IR
- Post-layout closure with the designer
Analog IC verification
Own the evidence that a block meets its specification. Full corner coverage, statistical analysis and model validation — with regression decks your team can re-run without you.
- Full corner, temperature and mismatch sweeps
- Monte Carlo and statistical coverage
- Model validation and regression decks
06 / Contact
Send us your spec
The spec, the schematic, or the plot that doesn’t look right. We read it and reply within three working days with the real constraint, a fixed scope, a schedule and a price.
Porto, Portugal
Visits by appointment. We travel for kick-off and for bring-up.Mutual NDA on request